• Investigated band to hopping electronic transport in crystalline oxide semiconductors (WO₃, W doped Indium oxide, etc.).
• Conducted low-temperature, and gate-bias dependent Hall measurements in semiconducting oxides.
• Designed the process flow and fabricated electronic test structures on oxide semiconductors, and wire-bonded them.
• Developed process for wire-bonding to ultra-thin semiconductors.
• Collaborated and contributed to experimental workflows within a 9-partner EU consortium project CONCEPT Project

• Integrated ferroelectric materials with 2D FETs for low-power logic and memory functionalities.
• Engineered phase-change ferroelectric effect in the gate stack using HfO₂ to surpass the Boltzmann limit for enabling steep-switching FETs.
• Used high speed and low temperature electrical measurements to study fluctuations in ferroelectric FETs.

Thesis: Engineering Nano-Electronic Devices using 2-D Materials: CMOS Logic to Biosensing

• Led end-to-end development of 2D-material FETs — TCAD modeling, design, fabrication, and characterization — to advance next-generation CMOS logic and memory technologies.
  • Realized 30 nm channel lengths through optimized process & proximity correction in e-beam lithography.
  • Developed sub-thermionic MoS₂ phase-FET (SS_min = 8.5 mV/dec) by BEOL integration of nickel ferrite with filamentary threshold switching.
  • Engineered low resistance, highly reliable, and high yield Ni-MoS₂ contacts (R_C = 1.3 kΩ μm)
  • Optimized functionalization-free top-gate ALD Al₂O₃ dielectrics on MoS₂.
  • Defined and fabricated test structures for measuring electrical parameters of 2D materials and their devices.
  • Characterized (electrical, material) FETs, ISFETs, and MOSCAPs. Extracted device performance metrics.
  • Python-based extraction and statistical analysis of performance metrics from devices.
• Development of 2D-material ISFETs — from TCAD modeling, design, fabrication, process integration, and characterization — for scalable and CMOS-compatible pH and biosensing applications.
  • Realized super-Nernstian ISFETs surpassing the Nernst limit (S_V = 362 mV/pH) based on WSe₂/MoS₂ heterostructures.
  • Developed MoS₂ based enzymatic bio-FETs for sensing total-cholesterol.
• Designed, developed, and calibrated physics-based TCAD models for FET and ISFET device simulations.
  • Simulated experimentally calibrated WSe₂/MoS₂ heterostructures ISFET in TCAD.
  • Numerically modeled ferroelectric negative capacitance and combined them with TCAD simulations to demonstrate NC-FETs for steep-switching logic and NC-ISFETs for highly sensitive sensors.
• Mentored 1 Ph.D. student and 1 undergraduate summer intern.

• Point of contact for SoC-level automatic test pattern generation (ATPG) activities for stuck-at and IDDQ faults testing.
• Performed scan-extraction, design rule checking (DRC), and achieved coverage targets (99.25%).
• Generated ATPG test patterns and supported post-silicon validation.
• I was promoted to Engineer after 1 year of experience.

• Studied and developed fully layered test benches for functional verification of designs and systems using System Verilog.